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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-20 07:47:14 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-10-28 07:46:53 -0700 |
| commit | e6e03dcffd3583f6fd8148108e65d514b8382c2c (patch) | |
| tree | 22ea70c5fb7ee07ce8f3afd6944346fcffd45725 /target/riscv | |
| parent | 9bb73502321d46f4d320fa17aa38201445783fc4 (diff) | |
| download | qemu-e6e03dcffd3583f6fd8148108e65d514b8382c2c.zip qemu-e6e03dcffd3583f6fd8148108e65d514b8382c2c.tar.gz qemu-e6e03dcffd3583f6fd8148108e65d514b8382c2c.tar.bz2 | |
riscv: Skip checking CSR privilege level in debugger mode
If we are in debugger mode, skip the CSR privilege level checking
so that we can read/write all CSRs. Otherwise we get:
(gdb) p/x $mtvec
Could not fetch register "mtvec"; remote failure reply 'E14'
when the hart is currently in S-mode.
Reported-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/csr.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f767ad2..974c9c2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -801,7 +801,10 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, #if !defined(CONFIG_USER_ONLY) int csr_priv = get_field(csrno, 0x300); int read_only = get_field(csrno, 0xC00) == 3; - if ((write_mask && read_only) || (env->priv < csr_priv)) { + if ((!env->debugger) && (env->priv < csr_priv)) { + return -1; + } + if (write_mask && read_only) { return -1; } #endif |