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authorBin Meng <bmeng@tinylab.org>2023-02-28 21:45:33 +0800
committerPalmer Dabbelt <palmer@rivosinc.com>2023-03-01 16:40:24 -0800
commite4e1f216a1ece6a69d10b22bc6f1cf855e054c95 (patch)
treed067b279678fd879c84e761963b18760f67f8442 /target/riscv
parent0308fc621914ba424705d188dc4a58006edb3472 (diff)
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target/riscv: Allow debugger to access sstc CSRs
At present with a debugger attached sstc CSRs can only be accssed when CPU is in M-mode, or configured correctly. Fix it by adjusting their predicate() routine logic so that the static config check comes before the run-time check, as well as adding a debugger check. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230228104035.1879882-17-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/csr.c19
1 files changed, 14 insertions, 5 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a0e70f5..020c3f5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -952,6 +952,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
+ hmode_check = true;
+ }
+
+ RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
}
@@ -972,11 +985,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
}
- if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
- hmode_check = true;
- }
-
- return hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ return RISCV_EXCP_NONE;
}
static RISCVException sstc_32(CPURISCVState *env, int csrno)