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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-07-19 09:39:49 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-07-21 07:47:05 -1000 |
| commit | b5cf74284166c1ecd119388c31b6eca8e1d7b4a6 (patch) | |
| tree | cbb8ecfd7057eaa56aefffacc5867bcbd57e3fa0 /target/riscv | |
| parent | 10c37828b213cd490bd20e243916e96f5d588c8d (diff) | |
| download | qemu-b5cf74284166c1ecd119388c31b6eca8e1d7b4a6.zip qemu-b5cf74284166c1ecd119388c31b6eca8e1d7b4a6.tar.gz qemu-b5cf74284166c1ecd119388c31b6eca8e1d7b4a6.tar.bz2 | |
accel/tcg: Remove TranslatorOps.breakpoint_check
The hook is now unused, with breakpoints checked outside translation.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/translate.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index deda0c8..6983be5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -961,22 +961,6 @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } -static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx = container_of(dcbase, DisasContext, base); - - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - ctx->base.is_jmp = DISAS_NORETURN; - gen_exception_debug(); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next += 4; - return true; -} - static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); @@ -1029,7 +1013,6 @@ static const TranslatorOps riscv_tr_ops = { .init_disas_context = riscv_tr_init_disas_context, .tb_start = riscv_tr_tb_start, .insn_start = riscv_tr_insn_start, - .breakpoint_check = riscv_tr_breakpoint_check, .translate_insn = riscv_tr_translate_insn, .tb_stop = riscv_tr_tb_stop, .disas_log = riscv_tr_disas_log, |