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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-04-19 16:18:06 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:06 +1000 |
| commit | ed6eebaaafd3b96cc4ef3dcc30eb3a26c20ece57 (patch) | |
| tree | ebb36571131c83ee494cb20afd4794ed6329f436 /target/riscv | |
| parent | 8ab6d3fbfe1523c6cf53e6a38a62bff3c5e6ff3c (diff) | |
| download | qemu-ed6eebaaafd3b96cc4ef3dcc30eb3a26c20ece57.zip qemu-ed6eebaaafd3b96cc4ef3dcc30eb3a26c20ece57.tar.gz qemu-ed6eebaaafd3b96cc4ef3dcc30eb3a26c20ece57.tar.bz2 | |
target/riscv: Add ePMP support for the Ibex CPU
The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 66787d0..4bf6a00 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -202,6 +202,7 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, RV32 | RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); qdev_prop_set_bit(DEVICE(obj), "mmu", false); + qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); } static void rv32_imafcu_nommu_cpu_init(Object *obj) |