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authorAlistair Francis <alistair.francis@wdc.com>2021-04-24 13:34:37 +1000
committerAlistair Francis <alistair.francis@wdc.com>2021-05-11 20:02:07 +1000
commitc30a0757f094c107e491820e3d35224eb68859c7 (patch)
treec7f425b5df001b5947efd027d1a4b16fec69c2f0 /target/riscv
parent6baba30ad0b7fbad035a530cc8d0a16c9cc74dc9 (diff)
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target/riscv: Fix the RV64H decode comment
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/insn32.decode2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fecf0f1..8901ba1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
-# *** RV32H Base Instruction Set ***
+# *** RV64H Base Instruction Set ***
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s