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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:45 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | b5c042e8a0300989b7e9ce0d24b6535c77439d3e (patch) | |
| tree | 9d5865c4f7d000babb9b5c39aa4a3207839d1a7f /target/riscv | |
| parent | e17801e1708da60371550af5a67e14c7d8db4eae (diff) | |
| download | qemu-b5c042e8a0300989b7e9ce0d24b6535c77439d3e.zip qemu-b5c042e8a0300989b7e9ce0d24b6535c77439d3e.tar.gz qemu-b5c042e8a0300989b7e9ce0d24b6535c77439d3e.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_h
Create a new "h" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are
replaced with riscv_has_ext(env, RVH).
Remove the old "h" property and 'ext_h' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 10 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 |
2 files changed, 5 insertions, 6 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9565495..6291224 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -847,13 +847,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers"); return; } - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } @@ -1172,7 +1172,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) if (riscv_has_ext(env, RVU)) { ext |= RVU; } - if (riscv_cpu_cfg(env)->ext_h) { + if (riscv_has_ext(env, RVH)) { ext |= RVH; } if (riscv_cpu_cfg(env)->ext_v) { @@ -1509,6 +1509,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { .misa_bit = RVS, .enabled = true}, {.name = "u", .description = "User-level instructions", .misa_bit = RVU, .enabled = true}, + {.name = "h", .description = "Hypervisor", + .misa_bit = RVH, .enabled = true}, }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1533,7 +1535,6 @@ static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), @@ -1647,7 +1648,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext != 0) { cpu->cfg.ext_v = misa_ext & RVV; - cpu->cfg.ext_h = misa_ext & RVH; cpu->cfg.ext_j = misa_ext & RVJ; /* diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4860615..823be82 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { struct RISCVCPUConfig { bool ext_g; - bool ext_h; bool ext_j; bool ext_v; bool ext_zba; |