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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-04-06 15:03:42 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 1a36e23a62283ecca1b56a983cfce67e4ec84ee7 (patch) | |
| tree | 4fc0996b539c81f9a2ada4d426ded5a92114f4ab /target/riscv | |
| parent | 427d8e7dd871a747727dbbfef22041fedef2ee32 (diff) | |
| download | qemu-1a36e23a62283ecca1b56a983cfce67e4ec84ee7.zip qemu-1a36e23a62283ecca1b56a983cfce67e4ec84ee7.tar.gz qemu-1a36e23a62283ecca1b56a983cfce67e4ec84ee7.tar.bz2 | |
target/riscv: remove cpu->cfg.ext_m
Create a new "m" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are
replaced with riscv_has_ext(env, RVM).
Remove the old "m" property and 'ext_m' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 10 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 |
2 files changed, 5 insertions, 6 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 33db4fa..2464045 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -817,13 +817,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) CPURISCVState *env = &cpu->env; /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_m = true; cpu->cfg.ext_icsr = true; cpu->cfg.ext_ifencei = true; @@ -1153,7 +1153,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) if (riscv_has_ext(env, RVE)) { ext |= RVE; } - if (riscv_cpu_cfg(env)->ext_m) { + if (riscv_has_ext(env, RVM)) { ext |= RVM; } if (riscv_has_ext(env, RVA)) { @@ -1505,6 +1505,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { .misa_bit = RVI, .enabled = true}, {.name = "e", .description = "Base integer instruction set (embedded)", .misa_bit = RVE, .enabled = false}, + {.name = "m", .description = "Integer multiplication and division", + .misa_bit = RVM, .enabled = true}, }; static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1528,7 +1530,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext != 0) { - cpu->cfg.ext_m = misa_ext & RVM; cpu->cfg.ext_v = misa_ext & RVV; cpu->cfg.ext_s = misa_ext & RVS; cpu->cfg.ext_u = misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2b42de6..71540a3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { struct RISCVCPUConfig { bool ext_g; - bool ext_m; bool ext_s; bool ext_u; bool ext_h; |