diff options
author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2023-04-12 13:43:11 +0200 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
commit | ebd476488d1369d602534e82234d410ca1734f07 (patch) | |
tree | fec83b0e97644c01a3e50861b9c8cd721897cb2a /target/riscv/translate.c | |
parent | 42967f40731c197cb8e59ad8ac480a2dcc80c199 (diff) | |
download | qemu-ebd476488d1369d602534e82234d410ca1734f07.zip qemu-ebd476488d1369d602534e82234d410ca1734f07.tar.gz qemu-ebd476488d1369d602534e82234d410ca1734f07.tar.bz2 |
target/riscv: Encode the FS and VS on a normal way for tb flags
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a
normal way.
It will make it hard to change the tb flags layout. And even worse, if we
want to keep tb flags for a same extension togather without a hole.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com>
[rth: Adjust trans_rvf.c.inc as well; use the typedef]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
-rw-r--r-- | target/riscv/translate.c | 32 |
1 files changed, 14 insertions, 18 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ebd0052..411e771 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,10 +64,10 @@ typedef struct DisasContext { RISCVMXL xl; uint32_t misa_ext; uint32_t opcode; - uint32_t mstatus_fs; - uint32_t mstatus_vs; - uint32_t mstatus_hs_fs; - uint32_t mstatus_hs_vs; + RISCVExtStatus mstatus_fs; + RISCVExtStatus mstatus_vs; + RISCVExtStatus mstatus_hs_fs; + RISCVExtStatus mstatus_hs_vs; uint32_t mem_idx; /* * Remember the rounding mode encoded in the previous fp instruction, @@ -601,8 +601,6 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) #ifndef CONFIG_USER_ONLY /* - * The states of mstatus_fs are: - * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. */ @@ -614,9 +612,9 @@ static void mark_fs_dirty(DisasContext *ctx) return; } - if (ctx->mstatus_fs != MSTATUS_FS) { + if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { /* Remember the state change for the rest of the TB. */ - ctx->mstatus_fs = MSTATUS_FS; + ctx->mstatus_fs = EXT_STATUS_DIRTY; tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); @@ -624,9 +622,9 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); } - if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { + if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) { /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_fs = MSTATUS_FS; + ctx->mstatus_hs_fs = EXT_STATUS_DIRTY; tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); @@ -640,8 +638,6 @@ static inline void mark_fs_dirty(DisasContext *ctx) { } #ifndef CONFIG_USER_ONLY /* - * The states of mstatus_vs are: - * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. */ @@ -649,9 +645,9 @@ static void mark_vs_dirty(DisasContext *ctx) { TCGv tmp; - if (ctx->mstatus_vs != MSTATUS_VS) { + if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { /* Remember the state change for the rest of the TB. */ - ctx->mstatus_vs = MSTATUS_VS; + ctx->mstatus_vs = EXT_STATUS_DIRTY; tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); @@ -659,9 +655,9 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); } - if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { + if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) { /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_vs = MSTATUS_VS; + ctx->mstatus_hs_vs = EXT_STATUS_DIRTY; tmp = tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); @@ -1168,8 +1164,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->pc_succ_insn = ctx->base.pc_first; ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); - ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; - ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; + ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); + ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); ctx->priv_ver = env->priv_ver; ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); ctx->misa_ext = env->misa_ext; |