diff options
| author | Christoph Muellner <cmuellner@linux.com> | 2023-02-24 10:25:34 -0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-05 11:49:20 -0800 |
| commit | a939c500793ae7672defe5e3dc83220576a7b202 (patch) | |
| tree | 6565b989712d950973e8b7a3edb239c8c8b6898b /target/riscv/translate.c | |
| parent | 2946e1af2704bf6584f57d4e3aec49d1d5f3ecc0 (diff) | |
| download | qemu-a939c500793ae7672defe5e3dc83220576a7b202.zip qemu-a939c500793ae7672defe5e3dc83220576a7b202.tar.gz qemu-a939c500793ae7672defe5e3dc83220576a7b202.tar.bz2 | |
target/riscv: implement Zicboz extension
The RISC-V base cache management operation (CBO) ISA extension has been
ratified. It defines three extensions: Cache-Block Management, Cache-Block
Prefetch and Cache-Block Zero. More information about the spec can be
found at [1].
Let's start by implementing the Cache-Block Zero extension, Zicboz. It
uses the cbo.zero instruction that, as with all CBO instructions that
will be added later, needs to be implemented in an overlap group with
the LQ instruction due to overlapping patterns.
cbo.zero throws a Illegal Instruction/Virtual Instruction exception
depending on CSR state. This is also the case for the remaining cbo
instructions we're going to add next, so create a check_zicbo_envcfg()
that will be used by all Zicbo[mz] instructions.
[1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Christoph Muellner <cmuellner@linux.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a8d516c..fa8bd79 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1105,6 +1105,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzicond.c.inc" #include "insn_trans/trans_rvzawrs.c.inc" +#include "insn_trans/trans_rvzicbo.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_privileged.c.inc" |