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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 16:49:15 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | 86d0c457396b1a789fe2740f7bd8d476ea426298 (patch) | |
| tree | 3686d6412105f9001154d72b264169300da395c6 /target/riscv/translate.c | |
| parent | ea7b5d5af6c3f994b10caa80c7f41964678eb2bb (diff) | |
| download | qemu-86d0c457396b1a789fe2740f7bd8d476ea426298.zip qemu-86d0c457396b1a789fe2740f7bd8d476ea426298.tar.gz qemu-86d0c457396b1a789fe2740f7bd8d476ea426298.tar.bz2 | |
target/riscv: Fixup setting GVA
In preparation for adding support for the illegal instruction address
let's fixup the Hypervisor extension setting GVA logic and improve the
variable names.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-3-alistair.francis@opensource.wdc.com
Diffstat (limited to 'target/riscv/translate.c')
0 files changed, 0 insertions, 0 deletions