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| author | Yi Chen <chenyi2000@zju.edu.cn> | 2023-04-06 18:15:59 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | d6db7c975e2e0d60850043ea8f208dd446a61d0a (patch) | |
| tree | 6ffce401b6785a47d3836dd9aad0691f0e98509f /target/riscv/op_helper.c | |
| parent | 9ba63f9442067729c3fe41c88b1eb414874d46ea (diff) | |
| download | qemu-d6db7c975e2e0d60850043ea8f208dd446a61d0a.zip qemu-d6db7c975e2e0d60850043ea8f208dd446a61d0a.tar.gz qemu-d6db7c975e2e0d60850043ea8f208dd446a61d0a.tar.bz2 | |
target/riscv: fix H extension TVM trap
- Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
- Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
- Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
- Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
SFENCE.VMA/SINVAL.VMA or VS-mode executes SFENCE.VMA/SINVAL.VMA with
HSTATUS.VTVM enabled.
- Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes
HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA.
Signed-off-by: Yi Chen <chenyi2000@zju.edu.cn>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406101559.39632-1-chenyi2000@zju.edu.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/op_helper.c')
| -rw-r--r-- | target/riscv/op_helper.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index bd21c6e..0c10dd7 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -381,12 +381,12 @@ void helper_wfi(CPURISCVState *env) void helper_tlb_flush(CPURISCVState *env) { CPUState *cs = env_cpu(env); - if (!(env->priv >= PRV_S) || - (env->priv == PRV_S && - get_field(env->mstatus, MSTATUS_TVM))) { + if (!env->virt_enabled && + (env->priv == PRV_U || + (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_has_ext(env, RVH) && env->virt_enabled && - get_field(env->hstatus, HSTATUS_VTVM)) { + } else if (env->virt_enabled && + (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); } else { tlb_flush(cs); @@ -403,7 +403,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs = env_cpu(env); - if (env->priv == PRV_S && env->virt_enabled) { + if (env->virt_enabled) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC()); } |