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| author | Atish Patra <atish.patra@wdc.com> | 2022-06-20 16:15:57 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
| commit | 3780e33732f88a88b444fa42d56c5938ecd33e21 (patch) | |
| tree | 62d67457f6656bef463d743a02bc881ed1ff431c /target/riscv/meson.build | |
| parent | 621f35bb2fa8babb9ab2a65033fe8d47ea5cd8ba (diff) | |
| download | qemu-3780e33732f88a88b444fa42d56c5938ecd33e21.zip qemu-3780e33732f88a88b444fa42d56c5938ecd33e21.tar.gz qemu-3780e33732f88a88b444fa42d56c5938ecd33e21.tar.bz2 | |
target/riscv: Support mcycle/minstret write operation
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret through generic counter infrastructure.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-8-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/meson.build')
| -rw-r--r-- | target/riscv/meson.build | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 096249f..2c1975e 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -30,7 +30,8 @@ riscv_softmmu_ss.add(files( 'pmp.c', 'debug.c', 'monitor.c', - 'machine.c' + 'machine.c', + 'pmu.c' )) target_arch += {'riscv': riscv_ss} |