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| author | Atish Patra <atishp@rivosinc.com> | 2022-08-24 15:13:56 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-07 09:19:15 +0200 |
| commit | 43888c2f1823212b1064a6a94d65d8acaf954478 (patch) | |
| tree | f9cccb009819382f3133fe9a2516f3420fc9acb4 /target/riscv/machine.c | |
| parent | 7cbcc538f4b3040db1e39a6547efa501a8a44907 (diff) | |
| download | qemu-43888c2f1823212b1064a6a94d65d8acaf954478.zip qemu-43888c2f1823212b1064a6a94d65d8acaf954478.tar.gz qemu-43888c2f1823212b1064a6a94d65d8acaf954478.tar.bz2 | |
target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/machine.c')
| -rw-r--r-- | target/riscv/machine.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/machine.c b/target/riscv/machine.c index b508b04..622ffac 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -359,6 +359,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), VMSTATE_UINT64(env.mtohost, RISCVCPU), + VMSTATE_UINT64(env.stimecmp, RISCVCPU), VMSTATE_END_OF_LIST() }, |