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| author | Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> | 2022-01-06 22:01:07 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:10 +1000 |
| commit | 7934fdeee75c8d8ca02a396afc549e3f54303859 (patch) | |
| tree | f033a5e34b92d44e096b99852495ab960e3c1c24 /target/riscv/machine.c | |
| parent | 961738ffea964daad464389b3f06dd5b245fdf3c (diff) | |
| download | qemu-7934fdeee75c8d8ca02a396afc549e3f54303859.zip qemu-7934fdeee75c8d8ca02a396afc549e3f54303859.tar.gz qemu-7934fdeee75c8d8ca02a396afc549e3f54303859.tar.bz2 | |
target/riscv: modification of the trans_csrxx for 128-bit support
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-18-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/machine.c')
0 files changed, 0 insertions, 0 deletions