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| author | Yifei Jiang <jiangyifei@huawei.com> | 2020-10-26 19:55:26 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 07:17:23 -0800 |
| commit | f7697f0e629eb75d411bc6f314c6fff68fa4c238 (patch) | |
| tree | 51da5a47ea36ea88aa2b44799b6ab2eab912a0a0 /target/riscv/internals.h | |
| parent | 284d697c74ef3f4210cbccc5cd6b4894740e4ab3 (diff) | |
| download | qemu-f7697f0e629eb75d411bc6f314c6fff68fa4c238.zip qemu-f7697f0e629eb75d411bc6f314c6fff68fa4c238.tar.gz qemu-f7697f0e629eb75d411bc6f314c6fff68fa4c238.tar.bz2 | |
target/riscv: Add basic vmstate description of CPU
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/internals.h')
| -rw-r--r-- | target/riscv/internals.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/internals.h b/target/riscv/internals.h index f1a546d..b15ad39 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -38,6 +38,10 @@ target_ulong fclass_d(uint64_t frs1); #define SEW32 2 #define SEW64 3 +#ifndef CONFIG_USER_ONLY +extern const VMStateDescription vmstate_riscv_cpu; +#endif + static inline uint64_t nanbox_s(float32 f) { return f | MAKE_64BIT_MASK(32, 32); |