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| author | Frank Chang <frank.chang@sifive.com> | 2021-12-10 15:56:55 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:53:31 +1000 |
| commit | e848a1e5632518647ac146d75b2fe006050ffb82 (patch) | |
| tree | a1f21ab3bef5677d97b67829c45c70038a0f082a /target/riscv/insn_trans | |
| parent | 719d3561b269d880b2d31e64ed7632407952bad0 (diff) | |
| download | qemu-e848a1e5632518647ac146d75b2fe006050ffb82.zip qemu-e848a1e5632518647ac146d75b2fe006050ffb82.tar.gz qemu-e848a1e5632518647ac146d75b2fe006050ffb82.tar.bz2 | |
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-70-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 53c8573..8fe7186 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2407,6 +2407,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ } GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN) /* Vector Floating-Point MIN/MAX Instructions */ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) |