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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-04-24 13:34:25 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:07 +1000 |
| commit | 6baba30ad0b7fbad035a530cc8d0a16c9cc74dc9 (patch) | |
| tree | c4aa021e8137ea987db04f0bc692c2178bb3e95f /target/riscv/insn_trans | |
| parent | daf866b606bdb94bb7c7ac6621353d30958521d8 (diff) | |
| download | qemu-6baba30ad0b7fbad035a530cc8d0a16c9cc74dc9.zip qemu-6baba30ad0b7fbad035a530cc8d0a16c9cc74dc9.tar.gz qemu-6baba30ad0b7fbad035a530cc8d0a16c9cc74dc9.tar.bz2 | |
target/riscv: Consolidate RV32/64 16-bit instructions
This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.
This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/insn_trans')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvi.c.inc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 1340676..bd93f63 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -24,6 +24,12 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a) return true; } +static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a) +{ + REQUIRE_64BIT(ctx); + return trans_illegal(ctx, a); +} + static bool trans_lui(DisasContext *ctx, arg_lui *a) { if (a->rd != 0) { |