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author | Kito Cheng <kito.cheng@sifive.com> | 2021-05-06 00:06:12 +0800 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2021-06-08 09:59:45 +1000 |
commit | e58529a8d03ab8e9127f3e7cdf757ff84af75698 (patch) | |
tree | f475f86e100c0961cb8c1dd43024fe565640a7f3 /target/riscv/insn_trans | |
parent | 91d8fc676819eff4ffcb7a8038e6de7d1dd381d3 (diff) | |
download | qemu-e58529a8d03ab8e9127f3e7cdf757ff84af75698.zip qemu-e58529a8d03ab8e9127f3e7cdf757ff84af75698.tar.gz qemu-e58529a8d03ab8e9127f3e7cdf757ff84af75698.tar.bz2 |
target/riscv: rvb: rotate (left/right)
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans')
-rw-r--r-- | target/riscv/insn_trans/trans_rvb.c.inc | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 2864032..429738d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -179,6 +179,24 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a) return gen_shifti(ctx, a, gen_sro); } +static bool trans_ror(DisasContext *ctx, arg_ror *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, tcg_gen_rotr_tl); +} + +static bool trans_rori(DisasContext *ctx, arg_rori *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, tcg_gen_rotr_tl); +} + +static bool trans_rol(DisasContext *ctx, arg_rol *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, tcg_gen_rotl_tl); +} + static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -290,3 +308,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) REQUIRE_EXT(ctx, RVB); return gen_shiftiw(ctx, a, gen_sro); } + +static bool trans_rorw(DisasContext *ctx, arg_rorw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_rorw); +} + +static bool trans_roriw(DisasContext *ctx, arg_roriw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_rorw); +} + +static bool trans_rolw(DisasContext *ctx, arg_rolw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_rolw); +} |