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| author | Frank Chang <frank.chang@sifive.com> | 2021-12-10 15:56:59 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:53:31 +1000 |
| commit | 5c89e9c0966dd423207bc477fcda9eb454d4308f (patch) | |
| tree | db5eb630e1f75cdecf433b24838c9dabc6fcdbd2 /target/riscv/insn32.decode | |
| parent | 34a2c2d81ad94ff910051b8b93b4aaff895cec88 (diff) | |
| download | qemu-5c89e9c0966dd423207bc477fcda9eb454d4308f.zip qemu-5c89e9c0966dd423207bc477fcda9eb454d4308f.tar.gz qemu-5c89e9c0966dd423207bc477fcda9eb454d4308f.tar.bz2 | |
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
Add supports of Vector unit-stride mask load/store instructions
(vlm.v, vsm.v), which has:
evl (effective vector length) = ceil(env->vl / 8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-74-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn32.decode')
0 files changed, 0 insertions, 0 deletions