diff options
| author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2022-10-13 14:29:43 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-06 10:42:55 +1000 |
| commit | 2c9d747121aa9f8f0494b9e3136a22a1c3a8b2a3 (patch) | |
| tree | 8cc47a138ce0357f917299a47c199dddeb2036e8 /target/riscv/debug.h | |
| parent | fb3f3730e405e2451dffc03c572037c2e0bd44c0 (diff) | |
| download | qemu-2c9d747121aa9f8f0494b9e3136a22a1c3a8b2a3.zip qemu-2c9d747121aa9f8f0494b9e3136a22a1c3a8b2a3.tar.gz qemu-2c9d747121aa9f8f0494b9e3136a22a1c3a8b2a3.tar.bz2 | |
target/riscv: Add itrigger support when icount is not enabled
When icount is not enabled, there is no API in QEMU that can get the
guest instruction number.
Translate the guest code in a way that each TB only has one instruction.
After executing the instruction, decrease the count by 1 until it reaches 0
where the itrigger fires.
Note that only when priviledge matches the itrigger configuration,
the count will decrease.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-2-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/debug.h')
| -rw-r--r-- | target/riscv/debug.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/riscv/debug.h b/target/riscv/debug.h index a1226b4..cc3358e 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -118,6 +118,17 @@ enum { SIZE_NUM = 16 }; +/* itrigger filed masks */ +#define ITRIGGER_ACTION 0x3f +#define ITRIGGER_U BIT(6) +#define ITRIGGER_S BIT(7) +#define ITRIGGER_PENDING BIT(8) +#define ITRIGGER_M BIT(9) +#define ITRIGGER_COUNT (0x3fff << 10) +#define ITRIGGER_HIT BIT(24) +#define ITRIGGER_VU BIT(25) +#define ITRIGGER_VS BIT(26) + bool tdata_available(CPURISCVState *env, int tdata_index); target_ulong tselect_csr_read(CPURISCVState *env); @@ -134,4 +145,5 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); void riscv_trigger_init(CPURISCVState *env); +bool riscv_itrigger_enabled(CPURISCVState *env); #endif /* RISCV_DEBUG_H */ |