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| author | Jim Wilson <jimw@sifive.com> | 2019-03-15 03:26:58 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-19 05:13:24 -0700 |
| commit | 753e3fe207db08ce0ef0405e8452c3397c9b9308 (patch) | |
| tree | 38d16fb6f1b727dafe750f2e4f638d50f0803132 /target/riscv/csr.c | |
| parent | 8e73df6aa3f2f0e5c26c03a94a88406616291815 (diff) | |
| download | qemu-753e3fe207db08ce0ef0405e8452c3397c9b9308.zip qemu-753e3fe207db08ce0ef0405e8452c3397c9b9308.tar.gz qemu-753e3fe207db08ce0ef0405e8452c3397c9b9308.tar.bz2 | |
RISC-V: Add debug support for accessing CSRs.
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190212230903.9215-1-jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/csr.c')
| -rw-r--r-- | target/riscv/csr.c | 32 |
1 files changed, 25 insertions, 7 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 960d2b0..9a40b4c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) static int fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - if (!(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { return -1; } #endif @@ -92,7 +92,7 @@ static int pmp(CPURISCVState *env, int csrno) static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { return -1; } #endif @@ -103,7 +103,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { return -1; } env->mstatus |= MSTATUS_FS; @@ -115,7 +115,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { return -1; } #endif @@ -126,7 +126,7 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) static int write_frm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { return -1; } env->mstatus |= MSTATUS_FS; @@ -138,7 +138,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val) static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { return -1; } #endif @@ -150,7 +150,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { return -1; } env->mstatus |= MSTATUS_FS; @@ -827,6 +827,24 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, return 0; } +/* + * Debugger support. If not in user mode, set env->debugger before the + * riscv_csrrw call and clear it after the call. + */ +int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, + target_ulong new_value, target_ulong write_mask) +{ + int ret; +#if !defined(CONFIG_USER_ONLY) + env->debugger = true; +#endif + ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); +#if !defined(CONFIG_USER_ONLY) + env->debugger = false; +#endif + return ret; +} + /* Control and Status Register function table */ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* User Floating-Point CSRs */ |