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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-04-24 13:33:18 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:07 +1000 |
| commit | 4fd7455bb39910c0730db66895328cd37b5cee5a (patch) | |
| tree | 6b206bc508ade207d502b77fd3da5093ce44a0c8 /target/riscv/csr.c | |
| parent | 994b6bb2db8d9d21207aa3a9991b9789c3d3d1ca (diff) | |
| download | qemu-4fd7455bb39910c0730db66895328cd37b5cee5a.zip qemu-4fd7455bb39910c0730db66895328cd37b5cee5a.tar.gz qemu-4fd7455bb39910c0730db66895328cd37b5cee5a.tar.bz2 | |
target/riscv: Remove the hardcoded MSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/csr.c')
| -rw-r--r-- | target/riscv/csr.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 41951a0..e955753 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -538,7 +538,11 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); - mstatus = set_field(mstatus, MSTATUS_SD, dirty); + if (riscv_cpu_is_32bit(env)) { + mstatus = set_field(mstatus, MSTATUS32_SD, dirty); + } else { + mstatus = set_field(mstatus, MSTATUS64_SD, dirty); + } env->mstatus = mstatus; return RISCV_EXCP_NONE; @@ -614,7 +618,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, } /* misa.MXL writes are not supported by QEMU */ - val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); + if (riscv_cpu_is_32bit(env)) { + val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL); + } else { + val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL); + } /* flush translation cache */ if (val != env->misa) { |