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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:01:54 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:45:29 -0800 |
| commit | c7b1bbc80fc2af17395d3986c346fd2307e57829 (patch) | |
| tree | efc0b420295dc152e2d5fa47dfd500a4611d6871 /target/riscv/cpu_user.h | |
| parent | ef6bb7b62682badefdcb744831510aaa5971684f (diff) | |
| download | qemu-c7b1bbc80fc2af17395d3986c346fd2307e57829.zip qemu-c7b1bbc80fc2af17395d3986c346fd2307e57829.tar.gz qemu-c7b1bbc80fc2af17395d3986c346fd2307e57829.tar.bz2 | |
target/riscv: Add the force HS exception mode
Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit
specifies if an exeption should be taken to HS mode no matter the
current delegation status. This is used when an exeption must be taken
to HS mode, such as when handling interrupts.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu_user.h')
0 files changed, 0 insertions, 0 deletions