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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-10-02 08:24:14 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-10-22 12:00:22 -0700 |
| commit | 69430111ab2fe3f32548a0e70437655d0d937a6a (patch) | |
| tree | c7f571d3674d172aa2fc5c61027e967068e0716a /target/riscv/cpu_helper.c | |
| parent | 4c5b97bfd0dd54dc27717ae8d1cd10e14eef1430 (diff) | |
| download | qemu-69430111ab2fe3f32548a0e70437655d0d937a6a.zip qemu-69430111ab2fe3f32548a0e70437655d0d937a6a.tar.gz qemu-69430111ab2fe3f32548a0e70437655d0d937a6a.tar.bz2 | |
riscv: Convert interrupt logs to use qemu_log_mask()
Currently we log interrupts and exceptions using the trace backend in
riscv_cpu_do_interrupt(). We also log exceptions using the interrupt log
mask (-d int) in riscv_raise_exception().
This patch converts riscv_cpu_do_interrupt() to log both interrupts and
exceptions with the interrupt log mask, so that both are printed when a
user runs QEMU with -d int.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 29a8c766c7c4748d0f2711c3a0abb81208138c5e.1601652179.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/cpu_helper.c')
| -rw-r--r-- | target/riscv/cpu_helper.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9048990..6c68239 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -895,7 +895,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) } trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, - riscv_cpu_get_trap_name(cause, async)); + riscv_cpu_get_trap_name(cause, async)); + + qemu_log_mask(CPU_LOG_INT, + "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", " + "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n", + __func__, env->mhartid, async, cause, env->pc, tval, + riscv_cpu_get_trap_name(cause, async)); if (env->priv <= PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { |