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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:01:51 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:45:28 -0800 |
| commit | ef6bb7b62682badefdcb744831510aaa5971684f (patch) | |
| tree | 1a72cc6a0b384718505cfbe69521b6bcddaa29c6 /target/riscv/cpu_bits.h | |
| parent | 205377f8940898e4c53d1b44350a3d4934a2da72 (diff) | |
| download | qemu-ef6bb7b62682badefdcb744831510aaa5971684f.zip qemu-ef6bb7b62682badefdcb744831510aaa5971684f.tar.gz qemu-ef6bb7b62682badefdcb744831510aaa5971684f.tar.bz2 | |
target/riscv: Add the virtulisation mode
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index eeaa03c..2cdb0de 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -430,6 +430,9 @@ #define PRV_H 2 /* Reserved */ #define PRV_M 3 +/* Virtulisation Register Fields */ +#define VIRT_ONOFF 1 + /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7fc00000 |