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| author | Alistair Francis <Alistair.Francis@wdc.com> | 2019-04-20 02:26:45 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-24 12:09:24 -0700 |
| commit | 356d74192a035c71a78a22d24812a6df6099ae40 (patch) | |
| tree | f018afe15828baacf3a3f484291bdf207143825f /target/riscv/cpu_bits.h | |
| parent | cd69e3a60b7c97127f56ceba566c5a3d594f42b5 (diff) | |
| download | qemu-356d74192a035c71a78a22d24812a6df6099ae40.zip qemu-356d74192a035c71a78a22d24812a6df6099ae40.tar.gz qemu-356d74192a035c71a78a22d24812a6df6099ae40.tar.bz2 | |
target/riscv: Mark privilege level 2 as reserved
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7180fcc..945aa8d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -383,7 +383,7 @@ /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 -#define PRV_H 2 +#define PRV_H 2 /* Reserved */ #define PRV_M 3 /* RV32 satp CSR field masks */ |