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| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2022-01-20 20:20:49 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:57 +1000 |
| commit | f310df58bd2c570be8b802bffb37cb30da0c346e (patch) | |
| tree | 13816edd3522a9ced3b1f4c41c69d55c2d5a93ef /target/riscv/cpu_bits.h | |
| parent | 5a2ae2350e78cfdc7ca9885b8c3d62137115a494 (diff) | |
| download | qemu-f310df58bd2c570be8b802bffb37cb30da0c346e.zip qemu-f310df58bd2c570be8b802bffb37cb30da0c346e.tar.gz qemu-f310df58bd2c570be8b802bffb37cb30da0c346e.tar.bz2 | |
target/riscv: Enable uxl field write
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5a6d49a..7c87433 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -449,6 +449,9 @@ typedef enum { #define COUNTEREN_IR (1 << 2) #define COUNTEREN_HPM3 (1 << 3) +/* vsstatus CSR bits */ +#define VSSTATUS64_UXL 0x0000000300000000ULL + /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 |