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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-08-12 12:13:16 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-08-25 09:11:35 -0700 |
| commit | 5a894dd7709f3b6a9f3e861dec71f78098bb3373 (patch) | |
| tree | 78e9b7a144a5b7ef20abc3af63f174645261fc58 /target/riscv/cpu_bits.h | |
| parent | 18df0b4695c06103f513dd6b0fb9d44482462bd5 (diff) | |
| download | qemu-5a894dd7709f3b6a9f3e861dec71f78098bb3373.zip qemu-5a894dd7709f3b6a9f3e861dec71f78098bb3373.tar.gz qemu-5a894dd7709f3b6a9f3e861dec71f78098bb3373.tar.bz2 | |
target/riscv: Allow setting a two-stage lookup in the virt status
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com
Message-Id: <08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8117e8b..ba0a5b5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -467,6 +467,7 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 +#define HS_TWO_STAGE 4 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 |