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| author | Frank Chang <frank.chang@sifive.com> | 2021-10-15 15:45:02 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2021-10-22 07:47:51 +1000 |
| commit | 61d56494884b0d4bbf78d0561258b3548dea3390 (patch) | |
| tree | 4e3c1d47d63a5a457c8413ca7c87a9b91d22adee /target/riscv/cpu_bits.h | |
| parent | 03fd0c5fe98f5617076527e9783d030294b64d6d (diff) | |
| download | qemu-61d56494884b0d4bbf78d0561258b3548dea3390.zip qemu-61d56494884b0d4bbf78d0561258b3548dea3390.tar.gz qemu-61d56494884b0d4bbf78d0561258b3548dea3390.tar.bz2 | |
target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211015074627.3957162-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
0 files changed, 0 insertions, 0 deletions