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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 20:43:29 -0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-09 15:08:53 -0800 |
| commit | 1c1c060aa866986ef8b7eb334abbb8c104a46e5c (patch) | |
| tree | 9870798361eec50c736fa4250b45ce357af3e622 /target/riscv/cpu.h | |
| parent | 3e5979046f3f5f65828d3950d0c3ec9846d63715 (diff) | |
| download | qemu-1c1c060aa866986ef8b7eb334abbb8c104a46e5c.zip qemu-1c1c060aa866986ef8b7eb334abbb8c104a46e5c.tar.gz qemu-1c1c060aa866986ef8b7eb334abbb8c104a46e5c.tar.bz2 | |
target/riscv: Remove the HS_TWO_STAGE flag
The HS_TWO_STAGE flag is no longer required as the MMU index contains
the information if we are performing a two stage access.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f514b128b1ff0fb41c85f914cee18f905007a922.1604464950.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5d8e54c..0cf48a1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -323,8 +323,7 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); -bool riscv_cpu_two_stage_lookup(CPURISCVState *env); -void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |