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| author | Frank Chang <frank.chang@sifive.com> | 2022-09-09 21:42:10 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-27 11:23:57 +1000 |
| commit | 9495c4888a80809ab9dba6d6e536b21c018c77a4 (patch) | |
| tree | 11f02f09ff1abbb2fef701bf75e5a5f173f79a3c /target/riscv/cpu.h | |
| parent | 9d5a84db91f12bd843206a57e0cde01e6a9d488d (diff) | |
| download | qemu-9495c4888a80809ab9dba6d6e536b21c018c77a4.zip qemu-9495c4888a80809ab9dba6d6e536b21c018c77a4.tar.gz qemu-9495c4888a80809ab9dba6d6e536b21c018c77a4.tar.bz2 | |
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs,
which allows us to support more types of triggers in the future.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20220909134215.1843865-4-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 73bcad3..b131fa8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -324,7 +324,11 @@ struct CPUArchState { /* trigger module */ target_ulong trigger_cur; - type2_trigger_t type2_trig[RV_MAX_TRIGGERS]; + target_ulong tdata1[RV_MAX_TRIGGERS]; + target_ulong tdata2[RV_MAX_TRIGGERS]; + target_ulong tdata3[RV_MAX_TRIGGERS]; + struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; + struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; /* machine specific rdtime callback */ uint64_t (*rdtime_fn)(void *); |