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| author | Dao Lu <daolu@rivosinc.com> | 2022-07-24 20:47:28 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-07 09:18:33 +0200 |
| commit | 4696f0ab5c436ed53567ce6baec67c921d9b70ae (patch) | |
| tree | 435b5069b3fb5f03bff74765763330893bc84f10 /target/riscv/cpu.h | |
| parent | 1ad3f9bdc76c83b23d689a111d5a160c528ac8ba (diff) | |
| download | qemu-4696f0ab5c436ed53567ce6baec67c921d9b70ae.zip qemu-4696f0ab5c436ed53567ce6baec67c921d9b70ae.tar.gz qemu-4696f0ab5c436ed53567ce6baec67c921d9b70ae.tar.bz2 | |
target/riscv: Add Zihintpause support
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Dao Lu <daolu@rivosinc.com>
Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 561d7fa..4be4b82 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,6 +426,7 @@ struct RISCVCPUConfig { bool ext_zkt; bool ext_ifencei; bool ext_icsr; + bool ext_zihintpause; bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; |