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| author | Michael Clark <mjc@sifive.com> | 2019-01-14 23:59:00 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-02-11 15:56:22 -0800 |
| commit | f18637cd611cd42bfe1eb4dafa337051fc4f6061 (patch) | |
| tree | aeec56acd8090e601a86f49b6b039df366a8d722 /target/riscv/cpu.h | |
| parent | d77c3401e694900a15dd8a658ae524f33fc8bc50 (diff) | |
| download | qemu-f18637cd611cd42bfe1eb4dafa337051fc4f6061.zip qemu-f18637cd611cd42bfe1eb4dafa337051fc4f6061.tar.gz qemu-f18637cd611cd42bfe1eb4dafa337051fc4f6061.tar.bz2 | |
RISC-V: Add misa runtime write support
This patch adds support for writing misa. misa is validated based
on rules in the ISA specification. 'E' is mutually exclusive with
all other extensions. 'D' depends on 'F' so 'D' bit is dropped
if 'F' is not present. A conservative approach to consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a97435b..5c2aebf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,7 +86,8 @@ so a cpu features bitfield is required, likewise for optional PMP support */ enum { RISCV_FEATURE_MMU, - RISCV_FEATURE_PMP + RISCV_FEATURE_PMP, + RISCV_FEATURE_MISA }; #define USER_VERSION_2_02_0 0x00020200 @@ -118,6 +119,7 @@ struct CPURISCVState { target_ulong user_ver; target_ulong priv_ver; target_ulong misa; + target_ulong misa_mask; uint32_t features; |