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| author | Anatoly Parshintsev <kupokupokupopo@gmail.com> | 2021-10-25 20:36:08 +0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-10-28 14:39:23 +1000 |
| commit | 0774a7a1ff24d6b8c2f90b9c341f057914b18134 (patch) | |
| tree | 467faaf11d482cbb9de419ace95645f2d6d886a1 /target/riscv/cpu.h | |
| parent | c655df7fe00669ac9ac3b0614be6e4a6f5782737 (diff) | |
| download | qemu-0774a7a1ff24d6b8c2f90b9c341f057914b18134.zip qemu-0774a7a1ff24d6b8c2f90b9c341f057914b18134.tar.gz qemu-0774a7a1ff24d6b8c2f90b9c341f057914b18134.tar.bz2 | |
target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-8-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b2422e3..3259082 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -410,6 +410,8 @@ FIELD(TB_FLAGS, HLSX, 10, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 13, 2) +/* If PointerMasking should be applied */ +FIELD(TB_FLAGS, PM_ENABLED, 15, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) |