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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-01-31 17:01:38 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:45:23 -0800 |
| commit | 028616130d5f0abc8a3b96f28963da51a875024b (patch) | |
| tree | cce777910468c573b1cdb5a494acf5c1743f200c /target/riscv/cpu.h | |
| parent | 8b6b68e05b43f976714ca1d2afe01a64e1d82cba (diff) | |
| download | qemu-028616130d5f0abc8a3b96f28963da51a875024b.zip qemu-028616130d5f0abc8a3b96f28963da51a875024b.tar.gz qemu-028616130d5f0abc8a3b96f28963da51a875024b.tar.bz2 | |
target/riscv: Convert MIP CSR to target_ulong
The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de0a8d8..95de9e5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -121,7 +121,7 @@ struct CPURISCVState { target_ulong mhartid; target_ulong mstatus; - uint32_t mip; + target_ulong mip; uint32_t miclaim; target_ulong mie; |