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| author | Atish Patra <atish.patra@wdc.com> | 2022-06-20 16:15:55 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-07-03 10:03:20 +1000 |
| commit | b1675eeb3e6e38b042a23a9647559c9c548c733d (patch) | |
| tree | bc5b0e5aa6ee899d84d2f2d63c172f315f618c3c /target/riscv/cpu.h | |
| parent | 18d6d89efc60f1c030c4a8a22816d2d911ece105 (diff) | |
| download | qemu-b1675eeb3e6e38b042a23a9647559c9c548c733d.zip qemu-b1675eeb3e6e38b042a23a9647559c9c548c733d.tar.gz qemu-b1675eeb3e6e38b042a23a9647559c9c548c733d.tar.bz2 | |
target/riscv: Implement mcountinhibit CSR
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ffee54e..0a916db 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -275,6 +275,8 @@ struct CPUArchState { target_ulong scounteren; target_ulong mcounteren; + target_ulong mcountinhibit; + target_ulong sscratch; target_ulong mscratch; |