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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-02-11 12:39:15 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-03-03 13:14:50 +1000 |
| commit | 89ffdcec2722c92aac99d1c2bd547ac9b2ff0179 (patch) | |
| tree | c7845f3dfec3629753b238ad800d3f732124e66e /target/riscv/cpu.h | |
| parent | aecabd50b7432e7173f51b2dd9d845717c6796ea (diff) | |
| download | qemu-89ffdcec2722c92aac99d1c2bd547ac9b2ff0179.zip qemu-89ffdcec2722c92aac99d1c2bd547ac9b2ff0179.tar.gz qemu-89ffdcec2722c92aac99d1c2bd547ac9b2ff0179.tar.bz2 | |
target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8183fb8..9ba0504 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -362,8 +362,12 @@ struct RISCVCPUConfig { bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; + bool ext_zdinx; bool ext_zfh; bool ext_zfhmin; + bool ext_zfinx; + bool ext_zhinx; + bool ext_zhinxmin; bool ext_zve32f; bool ext_zve64f; |