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| author | Joel Sing <joel@sing.id.au> | 2019-06-25 04:08:38 +1000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-06-25 22:37:04 -0700 |
| commit | c13b169f1a3dd158d6c75727cdc388f95988db39 (patch) | |
| tree | d23c2fd911b809c36128fa626e36076a31253826 /target/riscv/cpu.c | |
| parent | 591bddea8d874e1500921de0353818e5586618f5 (diff) | |
| download | qemu-c13b169f1a3dd158d6c75727cdc388f95988db39.zip qemu-c13b169f1a3dd158d6c75727cdc388f95988db39.tar.gz qemu-c13b169f1a3dd158d6c75727cdc388f95988db39.tar.bz2 | |
RISC-V: Clear load reservations on context switch and SC
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.
Signed-off-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 915b9e7..f8d07bd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -297,6 +297,7 @@ static void riscv_cpu_reset(CPUState *cs) env->pc = env->resetvec; #endif cs->exception_index = EXCP_NONE; + env->load_res = -1; set_default_nan_mode(1, &env->fp_status); } |