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| author | Palmer Dabbelt <palmer@sifive.com> | 2019-06-24 01:59:51 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-06-25 22:32:42 -0700 |
| commit | 591bddea8d874e1500921de0353818e5586618f5 (patch) | |
| tree | 89a3ca7210f98e3cdf6bd85ac83c228c87b28262 /target/riscv/cpu.c | |
| parent | 50fba816cd226001bec3e495c39879deb2fa5432 (diff) | |
| download | qemu-591bddea8d874e1500921de0353818e5586618f5.zip qemu-591bddea8d874e1500921de0353818e5586618f5.tar.gz qemu-591bddea8d874e1500921de0353818e5586618f5.tar.bz2 | |
RISC-V: Add support for the Zicsr extension
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu.c')
| -rw-r--r-- | target/riscv/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bbad39a..915b9e7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), |