Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf4' into staging

target/riscv: Convert to decodetree

Bastian: this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-15]:
    Many of the gen_* functions are called by the decode functions for 16-bit
    and 32-bit functions. If we move translation code from the gen_*
    functions to the generated trans_* functions of decode-tree, we get a lot of
    duplication. Therefore, we mostly generate calls to the old gen_* function
    which are properly replaced after step 2).

    Each of the trans_ functions are grouped into files corresponding to their
    ISA extension, e.g. addi which is in RV32I is translated in the file
    'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 16-18]:
    All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
    we convert the arguments in the 16 bit trans_ function to the arguments of
    the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 19-29]:
    this move all manual translation code into the trans_* instructions of
    decode tree, such that we can remove the old decode_* functions.

Palmer: This, with some additional cleanup patches, passed Alistar's
testing on rv32 and rv64 as well as my testing on rv64, so I think it's
good to go.  I've run my standard test against this exact tag.

I still don't have a Mac to try this on, sorry!

# gpg: Signature made Wed 13 Mar 2019 13:44:49 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
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* remotes/palmer/tags/riscv-for-master-4.0-sf4: (29 commits)
  target/riscv: Remove decode_RV32_64G()
  target/riscv: Remove gen_system()
  target/riscv: Rename trans_arith to gen_arith
  target/riscv: Remove manual decoding of RV32/64M insn
  target/riscv: Remove shift and slt insn manual decoding
  target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
  target/riscv: Move gen_arith_imm() decoding into trans_* functions
  target/riscv: Remove manual decoding from gen_store()
  target/riscv: Remove manual decoding from gen_load()
  target/riscv: Remove manual decoding from gen_branch()
  target/riscv: Remove gen_jalr()
  target/riscv: Convert quadrant 2 of RVXC insns to decodetree
  target/riscv: Convert quadrant 1 of RVXC insns to decodetree
  target/riscv: Convert quadrant 0 of RVXC insns to decodetree
  target/riscv: Convert RV priv insns to decodetree
  target/riscv: Convert RV64D insns to decodetree
  target/riscv: Convert RV32D insns to decodetree
  target/riscv: Convert RV64F insns to decodetree
  target/riscv: Convert RV32F insns to decodetree
  target/riscv: Convert RV64A insns to decodetree
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

1 files changed, 19 insertions, 0 deletions

diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 4072abe..9c6c109 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -1 +1,20 @@
 obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+
+decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
+decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
+
+target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
+	$(call quiet-command, \
+	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
+	  "GEN", $(TARGET_DIR)$@)
+
+target/riscv/decode_insn16.inc.c: \
+  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+	$(call quiet-command, \
+	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
+	  "GEN", $(TARGET_DIR)$@)
+
+target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
+	target/riscv/decode_insn16.inc.c