diff options
| author | Víctor Colombo <victor.colombo@eldorado.org.br> | 2022-05-04 18:05:35 -0300 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-05-05 15:36:17 -0300 |
| commit | 502423309159a4305f315e55ff6ec75aa61a91b0 (patch) | |
| tree | 4d2086844c95c46685146fdb570fec38e820711a /target/ppc | |
| parent | e4eea6ef667a9bf75114ad860d0e6b239b74b537 (diff) | |
| download | qemu-502423309159a4305f315e55ff6ec75aa61a91b0.zip qemu-502423309159a4305f315e55ff6ec75aa61a91b0.tar.gz qemu-502423309159a4305f315e55ff6ec75aa61a91b0.tar.bz2 | |
target/ppc: Remove msr_ep macro
msr_ep macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220504210541.115256-17-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/cpu.h | 2 | ||||
| -rw-r--r-- | target/ppc/helper_regs.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index cd672de..5e804f0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -363,6 +363,7 @@ FIELD(MSR, EE, MSR_EE, 1) FIELD(MSR, PR, MSR_PR, 1) FIELD(MSR, FP, MSR_FP, 1) FIELD(MSR, ME, MSR_ME, 1) +FIELD(MSR, EP, MSR_EP, 1) FIELD(MSR, IR, MSR_IR, 1) FIELD(MSR, DR, MSR_DR, 1) FIELD(MSR, DS, MSR_DS, 1) @@ -486,7 +487,6 @@ FIELD(MSR, LE, MSR_LE, 1) #define msr_fe0 ((env->msr >> MSR_FE0) & 1) #define msr_de ((env->msr >> MSR_DE) & 1) #define msr_fe1 ((env->msr >> MSR_FE1) & 1) -#define msr_ep ((env->msr >> MSR_EP) & 1) #define msr_ts ((env->msr >> MSR_TS1) & 3) #define DBCR0_ICMP (1 << 27) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index b150b78..97cd263 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -240,8 +240,8 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) /* Swap temporary saved registers with GPRs */ hreg_swap_gpr_tgpr(env); } - if (unlikely((value >> MSR_EP) & 1) != msr_ep) { - env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; + if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) { + env->excp_prefix = FIELD_EX64(value, MSR, EP) * 0xFFF00000; } /* * If PR=1 then EE, IR and DR must be 1 |