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| author | Tony Nguyen <tony.nguyen@bt.com> | 2019-08-24 04:10:58 +1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-03 08:30:38 -0700 |
| commit | 14776ab5a12972ea439c7fb2203a4c15a09094b4 (patch) | |
| tree | b53091625b410a722bf5f4e17a9631457994eed4 /target/ppc | |
| parent | fec105c2abda8567ec15230429c41429b5ee307c (diff) | |
| download | qemu-14776ab5a12972ea439c7fb2203a4c15a09094b4.zip qemu-14776ab5a12972ea439c7fb2203a4c15a09094b4.tar.gz qemu-14776ab5a12972ea439c7fb2203a4c15a09094b4.tar.bz2 | |
tcg: TCGMemOp is now accelerator independent MemOp
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.
Target dependant attributes are conditionalized upon NEED_CPU_H.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <81d9cd7d7f5aaadfa772d6c48ecee834e9cf7882.1566466906.git.tony.nguyen@bt.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/ppc')
| -rw-r--r-- | target/ppc/translate.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0cf3f97..adb8fd5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -163,7 +163,7 @@ struct DisasContext { int mem_idx; int access_type; /* Translation flags */ - TCGMemOp default_tcg_memop_mask; + MemOp default_tcg_memop_mask; #if defined(TARGET_PPC64) bool sf_mode; bool has_cfar; @@ -3142,7 +3142,7 @@ static void gen_isync(DisasContext *ctx) #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) -static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) +static void gen_load_locked(DisasContext *ctx, MemOp memop) { TCGv gpr = cpu_gpr[rD(ctx->opcode)]; TCGv t0 = tcg_temp_new(); @@ -3167,7 +3167,7 @@ LARX(lbarx, DEF_MEMOP(MO_UB)) LARX(lharx, DEF_MEMOP(MO_UW)) LARX(lwarx, DEF_MEMOP(MO_UL)) -static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, +static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, TCGv EA, TCGCond cond, int addend) { TCGv t = tcg_temp_new(); @@ -3193,7 +3193,7 @@ static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, tcg_temp_free(u); } -static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) +static void gen_ld_atomic(DisasContext *ctx, MemOp memop) { uint32_t gpr_FC = FC(ctx->opcode); TCGv EA = tcg_temp_new(); @@ -3306,7 +3306,7 @@ static void gen_ldat(DisasContext *ctx) } #endif -static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) +static void gen_st_atomic(DisasContext *ctx, MemOp memop) { uint32_t gpr_FC = FC(ctx->opcode); TCGv EA = tcg_temp_new(); @@ -3389,7 +3389,7 @@ static void gen_stdat(DisasContext *ctx) } #endif -static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) +static void gen_conditional_store(DisasContext *ctx, MemOp memop) { TCGLabel *l1 = gen_new_label(); TCGLabel *l2 = gen_new_label(); |