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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2017-07-18 01:55:35 -0300 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-07-19 14:45:16 -0700 |
| commit | e2622073e014b65e87134a3b32117ab170e91445 (patch) | |
| tree | 9f43bb7f7e77c8f701bc6ef28c2ae777c9d1cf50 /target/ppc/translate | |
| parent | 0d9acef24062844b96c671b4379d9fb03c3ea606 (diff) | |
| download | qemu-e2622073e014b65e87134a3b32117ab170e91445.zip qemu-e2622073e014b65e87134a3b32117ab170e91445.tar.gz qemu-e2622073e014b65e87134a3b32117ab170e91445.tar.bz2 | |
target/ppc: optimize various functions using extract op
Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20170718045540.16322-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/ppc/translate')
| -rw-r--r-- | target/ppc/translate/vsx-impl.inc.c | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 7f12908..85ed135 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1248,8 +1248,7 @@ static void gen_xsxexpdp(DisasContext *ctx) gen_exception(ctx, POWERPC_EXCP_VSXU); return; } - tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52); - tcg_gen_andi_i64(rt, rt, 0x7FF); + tcg_gen_extract_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52, 11); } static void gen_xsxexpqp(DisasContext *ctx) @@ -1262,8 +1261,7 @@ static void gen_xsxexpqp(DisasContext *ctx) gen_exception(ctx, POWERPC_EXCP_VSXU); return; } - tcg_gen_shri_i64(xth, xbh, 48); - tcg_gen_andi_i64(xth, xth, 0x7FFF); + tcg_gen_extract_i64(xth, xbh, 48, 15); tcg_gen_movi_i64(xtl, 0); } @@ -1323,8 +1321,7 @@ static void gen_xsxsigdp(DisasContext *ctx) zr = tcg_const_i64(0); nan = tcg_const_i64(2047); - tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52); - tcg_gen_andi_i64(exp, exp, 0x7FF); + tcg_gen_extract_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52, 11); tcg_gen_movi_i64(t0, 0x0010000000000000); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); @@ -1352,8 +1349,7 @@ static void gen_xsxsigqp(DisasContext *ctx) zr = tcg_const_i64(0); nan = tcg_const_i64(32767); - tcg_gen_shri_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48); - tcg_gen_andi_i64(exp, exp, 0x7FFF); + tcg_gen_extract_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48, 15); tcg_gen_movi_i64(t0, 0x0001000000000000); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); @@ -1448,10 +1444,8 @@ static void gen_xvxexpdp(DisasContext *ctx) gen_exception(ctx, POWERPC_EXCP_VSXU); return; } - tcg_gen_shri_i64(xth, xbh, 52); - tcg_gen_andi_i64(xth, xth, 0x7FF); - tcg_gen_shri_i64(xtl, xbl, 52); - tcg_gen_andi_i64(xtl, xtl, 0x7FF); + tcg_gen_extract_i64(xth, xbh, 52, 11); + tcg_gen_extract_i64(xtl, xbl, 52, 11); } GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300) @@ -1474,16 +1468,14 @@ static void gen_xvxsigdp(DisasContext *ctx) zr = tcg_const_i64(0); nan = tcg_const_i64(2047); - tcg_gen_shri_i64(exp, xbh, 52); - tcg_gen_andi_i64(exp, exp, 0x7FF); + tcg_gen_extract_i64(exp, xbh, 52, 11); tcg_gen_movi_i64(t0, 0x0010000000000000); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF); tcg_gen_or_i64(xth, xth, t0); - tcg_gen_shri_i64(exp, xbl, 52); - tcg_gen_andi_i64(exp, exp, 0x7FF); + tcg_gen_extract_i64(exp, xbl, 52, 11); tcg_gen_movi_i64(t0, 0x0010000000000000); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); |