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| author | Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> | 2017-01-06 11:44:44 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2017-01-31 10:10:13 +1100 |
| commit | 3398b7428ba3964f6150590cde46d45c68d2fc25 (patch) | |
| tree | cd08080d18dd0c742f9ad1a64677815a924672c7 /target/ppc/translate | |
| parent | 8ad901e55884055e0ec5ee7f47b955f42b66cb9a (diff) | |
| download | qemu-3398b7428ba3964f6150590cde46d45c68d2fc25.zip qemu-3398b7428ba3964f6150590cde46d45c68d2fc25.tar.gz qemu-3398b7428ba3964f6150590cde46d45c68d2fc25.tar.bz2 | |
target-ppc: Add xxinsertw instruction
xxinsertw: VSX Vector Insert Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/translate')
| -rw-r--r-- | target/ppc/translate/vsx-impl.inc.c | 5 | ||||
| -rw-r--r-- | target/ppc/translate/vsx-ops.inc.c | 1 |
2 files changed, 4 insertions, 2 deletions
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 7977f24..c9ba0f5 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1180,7 +1180,7 @@ static void gen_xxsldwi(DisasContext *ctx) tcg_temp_free_i64(xtl); } -#define VSX_EXTRACT(name) \ +#define VSX_EXTRACT_INSERT(name) \ static void gen_##name(DisasContext *ctx) \ { \ TCGv xt, xb; \ @@ -1208,7 +1208,8 @@ static void gen_##name(DisasContext *ctx) \ tcg_temp_free_i32(t0); \ } -VSX_EXTRACT(xxextractuw) +VSX_EXTRACT_INSERT(xxextractuw) +VSX_EXTRACT_INSERT(xxinsertw) #undef GEN_XX2FORM #undef GEN_XX3FORM diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c index 473d925..096d358 100644 --- a/target/ppc/translate/vsx-ops.inc.c +++ b/target/ppc/translate/vsx-ops.inc.c @@ -285,6 +285,7 @@ GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300), GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300), +GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300), #define GEN_XXSEL_ROW(opc3) \ GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \ |