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| author | Nicholas Piggin <npiggin@gmail.com> | 2021-05-01 17:24:35 +1000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-05-04 13:12:46 +1000 |
| commit | 526cdce771fa27c37b68fd235ff9f1caa0bdd563 (patch) | |
| tree | 17ecd66691cbeb0e317e767001362a637200a3d0 /target/ppc/translate.c | |
| parent | 8b7e6b07a46809a75b857d30ae47e697e0f9b724 (diff) | |
| download | qemu-526cdce771fa27c37b68fd235ff9f1caa0bdd563.zip qemu-526cdce771fa27c37b68fd235ff9f1caa0bdd563.tar.gz qemu-526cdce771fa27c37b68fd235ff9f1caa0bdd563.tar.bz2 | |
target/ppc: Add POWER10 exception model
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210501072436.145444-3-npiggin@gmail.com>
[dwg: Corrected tab indenting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/translate.c')
| -rw-r--r-- | target/ppc/translate.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a7c568c..a638120 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7731,7 +7731,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) #if defined(TARGET_PPC64) if (env->excp_model == POWERPC_EXCP_POWER7 || env->excp_model == POWERPC_EXCP_POWER8 || - env->excp_model == POWERPC_EXCP_POWER9) { + env->excp_model == POWERPC_EXCP_POWER9 || + env->excp_model == POWERPC_EXCP_POWER10) { qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); } |