diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2019-04-11 10:00:01 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-04-26 11:37:57 +1000 |
| commit | a2dd4e83e76ba9c0d432145059dd9e2b2a096e2b (patch) | |
| tree | 97554cc89ba0383a59e949cde23cddfefb409027 /target/ppc/mmu-hash64.h | |
| parent | 993aaf0c0003f7af1bf62c1c2d5cc3c0fe687f5b (diff) | |
| download | qemu-a2dd4e83e76ba9c0d432145059dd9e2b2a096e2b.zip qemu-a2dd4e83e76ba9c0d432145059dd9e2b2a096e2b.tar.gz qemu-a2dd4e83e76ba9c0d432145059dd9e2b2a096e2b.tar.bz2 | |
ppc/hash64: Rework R and C bit updates
With MT-TCG, we are now running translation in a racy way, thus
we need to mimic hardware when it comes to updating the R and
C bits, by doing byte stores.
The current "store_hpte" abstraction is ill suited for this, we
replace it with two separate callbacks for setting R and C.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190411080004.8690-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/mmu-hash64.h')
| -rw-r--r-- | target/ppc/mmu-hash64.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 5be7ad8..87729d4 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -10,8 +10,6 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, int mmu_idx); -void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex, - uint64_t pte0, uint64_t pte1); void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong pte_index, target_ulong pte0, target_ulong pte1); |