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| author | Nicholas Piggin <npiggin@gmail.com> | 2023-06-25 22:03:17 +1000 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2023-07-07 04:18:26 -0300 |
| commit | b25f2ffa19c0f4a79de0315d4eade36ce76b031c (patch) | |
| tree | e90345e0ba04072938c65fa5c4b7037deaccd11c /target/ppc/mmu-hash32.c | |
| parent | 6f967f4f7869cd393585946ed43427c626a15d40 (diff) | |
| download | qemu-b25f2ffa19c0f4a79de0315d4eade36ce76b031c.zip qemu-b25f2ffa19c0f4a79de0315d4eade36ce76b031c.tar.gz qemu-b25f2ffa19c0f4a79de0315d4eade36ce76b031c.tar.bz2 | |
target/ppc: Add TFMR SPR implementation with read and write helpers
TFMR is the Time Facility Management Register which is specific to
POWER CPUs, and used for the purpose of timebase management (generally
by firmware, not the OS).
Add helpers for the TFMR register, which will form part of the core
timebase facility model in future but for now behaviour is unchanged.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230625120317.13877-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc/mmu-hash32.c')
0 files changed, 0 insertions, 0 deletions