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| author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2021-12-17 17:57:13 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2021-12-17 17:57:13 +0100 |
| commit | 9193eaa901c54dbff4a91ea0b12a99e0135dbca1 (patch) | |
| tree | b4482db90ab74476c9d83ec2177f5853f26baafe /target/ppc/insn32.decode | |
| parent | 17868d81e0074905b2c1e414af6618570e8059eb (diff) | |
| download | qemu-9193eaa901c54dbff4a91ea0b12a99e0135dbca1.zip qemu-9193eaa901c54dbff4a91ea0b12a99e0135dbca1.tar.gz qemu-9193eaa901c54dbff4a91ea0b12a99e0135dbca1.tar.bz2 | |
target/ppc: Implement Vector Mask Move insns
Implement the following PowerISA v3.1 instructions:
mtvsrbm: Move to VSR Byte Mask
mtvsrhm: Move to VSR Halfword Mask
mtvsrwm: Move to VSR Word Mask
mtvsrdm: Move to VSR Doubleword Mask
mtvsrqm: Move to VSR Quadword Mask
mtvsrbmi: Move to VSR Byte Mask Immediate
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211203194229.746275-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'target/ppc/insn32.decode')
| -rw-r--r-- | target/ppc/insn32.decode | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 639ac22..f68931f 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -40,6 +40,10 @@ %ds_rtp 22:4 !function=times_2 @DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si +&DX_b vrt b +%dx_b 6:10 16:5 0:1 +@DX_b ...... vrt:5 ..... .......... ..... . &DX_b b=%dx_b + &DX rt d %dx_d 6:s10 16:5 0:1 @DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d @@ -413,6 +417,13 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN ## Vector Mask Manipulation Instructions +MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb +MTVSRHM 000100 ..... 10001 ..... 11001000010 @VX_tb +MTVSRWM 000100 ..... 10010 ..... 11001000010 @VX_tb +MTVSRDM 000100 ..... 10011 ..... 11001000010 @VX_tb +MTVSRQM 000100 ..... 10100 ..... 11001000010 @VX_tb +MTVSRBMI 000100 ..... ..... .......... 01010 . @DX_b + VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb |