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| author | Nicholas Piggin <npiggin@gmail.com> | 2023-05-15 19:26:50 +1000 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2023-05-27 10:06:26 -0300 |
| commit | 4ee5d2817ff18d10be887853d5e966247f0a0c30 (patch) | |
| tree | 82413699d5676e719f46c6a04024713faa871c16 /target/ppc/excp_helper.c | |
| parent | fbda88f7abdeed3ceebdd18de6909a52df756c1c (diff) | |
| download | qemu-4ee5d2817ff18d10be887853d5e966247f0a0c30.zip qemu-4ee5d2817ff18d10be887853d5e966247f0a0c30.tar.gz qemu-4ee5d2817ff18d10be887853d5e966247f0a0c30.tar.bz2 | |
target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward
This optional behavior was removed from the ISA in v3.0, see
Summary of Changes preface:
Data Storage Interrupt Status Register for Alignment Interrupt:
Simplifies the Alignment interrupt by remov- ing the Data Storage
Interrupt Status Register (DSISR) from the set of registers modified
by the Alignment interrupt.
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230515092655.171206-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc/excp_helper.c')
| -rw-r--r-- | target/ppc/excp_helper.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 199328f..fea9221 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1431,13 +1431,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* Get rS/rD and rA from faulting opcode */ - /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. - */ - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + /* Optional DSISR update was removed from ISA v3.0 */ + if (!(env->insns_flags2 & PPC2_ISA300)) { + /* Get rS/rD and rA from faulting opcode */ + /* + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. + */ + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { |