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author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2022-10-11 17:48:18 -0300 |
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committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-10-28 13:15:22 -0300 |
commit | 64a9b5eebef97d5b742b162625d5bc262be832ec (patch) | |
tree | 281e8b37830944a2179becc9fda9b590fbf2700c /target/ppc/excp_helper.c | |
parent | 788ff1ce44b813475ddcb95726bdd3afdaa40d6d (diff) | |
download | qemu-64a9b5eebef97d5b742b162625d5bc262be832ec.zip qemu-64a9b5eebef97d5b742b162625d5bc262be832ec.tar.gz qemu-64a9b5eebef97d5b742b162625d5bc262be832ec.tar.bz2 |
target/ppc: add power-saving interrupt masking logic to p8_next_unmasked_interrupt
Export p8_interrupt_powersave and use it in p8_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-19-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target/ppc/excp_helper.c')
-rw-r--r-- | target/ppc/excp_helper.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index b4afdc8..9fa75c5 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1692,28 +1692,28 @@ void ppc_cpu_do_interrupt(CPUState *cs) static int p8_next_unmasked_interrupt(CPUPPCState *env) { - bool async_deliver; + PowerPCCPU *cpu = env_archcpu(env); + CPUState *cs = CPU(cpu); + /* Ignore MSR[EE] when coming out of some power management states */ + bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; assert((env->pending_interrupts & P8_UNUSED_INTERRUPTS) == 0); + if (cs->halted) { + /* LPCR[PECE] controls which interrupts can exit power-saving mode */ + return p8_interrupt_powersave(env); + } + /* Machine check exception */ if (env->pending_interrupts & PPC_INTERRUPT_MCK) { return PPC_INTERRUPT_MCK; } - /* - * For interrupts that gate on MSR:EE, we need to do something a - * bit more subtle, as we need to let them through even when EE is - * clear when coming out of some power management states (in order - * for them to become a 0x100). - */ - async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset; - /* Hypervisor decrementer exception */ if (env->pending_interrupts & PPC_INTERRUPT_HDECR) { /* LPCR will be clear when not supported so this will work */ bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); - if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { + if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) { /* HDEC clears on delivery */ return PPC_INTERRUPT_HDECR; } @@ -1724,13 +1724,13 @@ static int p8_next_unmasked_interrupt(CPUPPCState *env) bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); /* HEIC blocks delivery to the hypervisor */ - if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && + if ((msr_ee && !(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) || (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { return PPC_INTERRUPT_EXT; } } - if (async_deliver != 0) { + if (msr_ee != 0) { /* Decrementer exception */ if (env->pending_interrupts & PPC_INTERRUPT_DECR) { return PPC_INTERRUPT_DECR; |